Reset pin design
How do you treat an SoC's reset pin on the board?
| Level | ●● onsite technical |
| Track | Embedded & wearables |
| Really testing | Robustness against ESD and glitches. |
Going deeper
Extra explanation that is not in the book: worked numbers, where people go wrong, and how to say it in the room.
Worked example. 10 kΩ pull-up with 100 nF at the pin: τ = 1 ms — glitches much shorter than that can't reset the part. A 100 Ω resistor in series with the button limits the discharge to about 33 mA instead of an arc across the contacts.
ESD reality. A user-accessible button may see 8 kV contact discharge (IEC 61000-4-2). Put the TVS at the button, where the charge enters — not at the SoC.
Debug probes and supervisors. The JTAG/SWD probe also drives reset. If the supervisor output is push-pull, the two fight. Use open-drain outputs, wired-OR, with one pull-up.
Where people go wrong
- Putting the filter cap at the supervisor and a long trace to the SoC — the trace picks up noise after the filter.
- Choosing a supervisor threshold inside the rail's tolerance band, so normal ripple resets the board.
Errata
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